DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 639

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2.4) FKEY is cleared to H'00 for protection.
(2.5) The value of the DPFR parameter must be checked to confirm the download result.
(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is
After download is completed and the user procedure program is running, the VBR setting can
be changed.
The notes on download are as follows.
In the download processing, the values of the general registers of the CPU are retained.
During the download processing, interrupts must not be generated. For details on the
relationship between download and interrupts, see section 17.7.1, Interrupts during
Programming/Erasing.
Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved
before setting the SCO bit to 1.
A recommended procedure for confirming the download result is shown below.
set to the FUBRA parameter for initialization.
• After the on-chip program storage area is returned to the user MAT space, execution
• Check the value of the DPFR parameter (one byte of start address of the download
• If the value of the DPFR parameter is the same as before downloading (e.g. H’FF), the
• If the value of the DPFR parameter is different from before downloading, check the SS
• The current frequency of the CPU clock is set to the FPEFEQ parameter (general
returns to the user procedure program.
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download
program selection and FKEY register setting were normal, respectively.
register R4). For the settable range of the FPEFEQ parameter, see section 21.3.1, Clock
Timing.
When the frequency is set out of this range, an error is returned to the FPFR parameter
of the initialization program and initialization is not performed. For details on the
frequency setting, see the description in section 17.4.3 (2.1), Flash
programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU).
Rev. 5.00 Mar. 06, 2009 Page 619 of 770
REJ09B0243-0500