DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 227

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.3.9
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests
and specifies whether to link A/D converter start requests with interrupt skipping operation. The
MTU2 has one TADCR in channel 4.
Initial value:
Bit
15, 14
13 to 8 —
7
6
Note:
R/W:
Bit:
*
Do not set to 1 when complementary PWM mode is not selected.
Bit Name
BF[1:0]
UT4AE
DT4AE
R/W
Timer A/D Converter Start Request Control Register (TADCR)
15
0
BF[1:0]
R/W
14
0
13
R
0
-
00
Initial
Value
All 0
0
0*
12
R
0
-
11
R
0
-
R/W
R/W
R
R/W
R/W
10
R
0
-
Description
TADCOBRA_4/TADCOBRB_4 Transfer Timing Select
Select the timing for transferring data from
TADCOBRA_4 and TADCOBRB_4 to TADCORA_4
and TADCORB_4.
For details, see table 9.29.
These bits are always read as 0. The write value should
always be 0.
Up-Count TRG4AN Enable
Enables or disables A/D converter start requests
(TRG4AN) during TCNT_4 up-count operation.
0: A/D converter start requests (TRG4AN) disabled
1: A/D converter start requests (TRG4AN) enabled
Down-Count TRG4AN Enable
Enables or disables A/D converter start requests
(TRG4AN) during TCNT_4 down-count operation.
0: A/D converter start requests (TRG4AN) disabled
1: A/D converter start requests (TRG4AN) enabled
Reserved
R
9
0
-
during TCNT_4 up-count operation
during TCNT_4 up-count operation
during TCNT_4 down-count operation
during TCNT_4 down-count operation
R
8
0
-
UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
R/W
7
0
R/W
0*
Rev. 5.00 Mar. 06, 2009 Page 207 of 770
6
R/W
5
0
R/W
0*
4
R/W
0*
3
REJ09B0243-0500
R/W
0*
2
R/W
0*
1
R/W
0*
0

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