DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 105

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6
When an exception other than resets occurs during decoding the instruction placed in a delay slot
or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in
table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the
exception is accepted.
Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions
[Legend]
√: Accepted
×: Not accepted
⎯: Does not occur
Notes: 1. Interrupt disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L
Occurrence Timing
Instruction in delay slot
Immediately after interrupt
disabled instruction*
2. An exception is accepted before the execution of a delayed branch instruction.
3. An exception is accepted after a delayed branch (between instructions in the delay slot
4. An exception is accepted after the execution of the next instruction of an interrupt
Cases when Exceptions are Accepted
However, when an address error or a slot illegal instruction exception occurs in the
delay slot of the RTE instruction, correct operation is not guaranteed.
and the branch destination).
disabled instruction (before the execution two instructions after an interrupt disabled
instruction).
1
Address
Error
×*
√
2
General
Illegal
Instruction
⎯
√
Slot Illegal
Instruction
×*
√
Exception
2
Rev. 5.00 Mar. 06, 2009 Page 85 of 770
Trap
Instruction
⎯
√
REJ09B0243-0500
Interrupt
×*
×*
3
4