DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 322

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17. A/D Converter Start Request Setting
Interrupt Skipping in Complementary PWM Mode:
Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up
to seven times by making settings in the timer interrupt skipping set register (TITCR).
Transfers from a buffer register to a temporary register or a compare register can be skipped in
coordination with interrupt skipping by making settings in the timer buffer transfer register
(TBTER). For the linkage with buffer registers, refer to description 3, Buffer Transfer Control
Linked with Interrupt Skipping, below.
A/D converter start requests generated by the A/D converter start request delaying function can
also be skipped in coordination with interrupt skipping by making settings in the timer A/D
converter request control register (TADCR). For the linkage with the A/D converter start request
delaying function, refer to section 9.4.9, A/D Converter Start Request Delaying Function.
The setting of the timer interrupt skipping setting register (TITCR) must be done while the
TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of registers TIER_3 and
TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare
match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN
bits to 0 to clear the skipping counter.
1. Example of Interrupt Skipping Operation Setting Procedure
Rev. 5.00 Mar. 06, 2009 Page 302 of 770
REJ09B0243-0500
In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3
compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than
channels 3 and 4.
When start requests using a TGRA_3 compare-match are specified, A/D conversion can be
started at the crest of the TCNT_3 count.
A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt
enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow
(trough), set the TTGE2 bit in TIER_4 to 1.
Figure 9.67 shows an example of the interrupt skipping operation setting procedure. Figure
9.68 shows the periods during which interrupt skipping count can be changed.