DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 125

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4.2
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
Since a different interrupt vector is allocated to each interrupt source, the exception handling
routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can
be allocated to individual on-chip peripheral modules in interrupt priority registers C to F and H to
M (IPRC to IPRF and IPRH to IPRM). On-chip peripheral module interrupt exception handling
sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of
the on-chip peripheral module interrupt that was accepted.
6.4.3
A user break interrupt has a priority level of 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3
to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see
section 7, User Break Controller (UBC).
Note: * The user break interrupt is not generated on the 32 Kbyte (SH71251A and SH71241A)
IRQn pins
(Acceptance of IRQn interrupt/
writing 0 after reading IRQnF = 1)
On-Chip Peripheral Module Interrupts
User Break Interrupt*
and 16 Kbyte (SH71250A and SH71240A) versions.
Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control
detection
detection
RESIRQn
Level
Edge
IRQSR.IRQnL
S
R
IRQCR.IRQn1S
IRQCR.IRQn0S
Q
Rev. 5.00 Mar. 06, 2009 Page 105 of 770
IRQSR.IRQnF
n = 3 to 0
REJ09B0243-0500
CPU interrupt
request