DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 302

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9. Initial Output in Complementary PWM Mode
Rev. 5.00 Mar. 06, 2009 Page 282 of 770
REJ09B0243-0500
Negative phase
Positive phase
In complementary PWM mode, the initial output is determined by the setting of bits OLSN
and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to
OLS3P in timer output control register 2 (TOCR2).
This initial output is the PWM pulse non-active level, and is output from when complementary
PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set
in the dead time register (TDDR). Figure 9.44 shows an example of the initial output in
complementary PWM mode.
An example of the waveform when the initial PWM duty value is smaller than the TDDR
value is shown in figure 9.45.
output
output
Figure 9.44 Example of Initial Output in Complementary PWM Mode (1)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
Complementary
PWM mode
(TMDR setting)
Initial output
TGRA_4
TCNT_3 and TCNT_4 values
TDDR
TCNT_3 and TCNT_4 count start
(TSTR setting)
Active level
Dead time
TCNT_3
TCNT_4
Active level
Time