DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 296

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3. Initialization
Table 9.56 Registers and Counters Requiring Initialization
Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and
Rev. 5.00 Mar. 06, 2009 Page 276 of 770
REJ09B0243-0500
Register/Counter
TGRC_3
TDDR
TCBR
TGRD_3, TGRC_4, TGRD_4
TCNT_4
In complementary PWM mode, there are six registers that must be initialized. In addition,
there is a register that specifies whether to generate dead time (it should be used only when
dead time generation should be disabled).
Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register
(TMDR), the following initial register values must be set.
TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM
carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer
register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier
cycle. Set dead time Td in the timer dead time data register (TDDR).
When dead time is not needed, the TDER bit in the timer dead time enable register (TDER)
should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1,
and TDDR should be set to 1.
Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and
TGRD_4.
The values set in the five buffer registers excluding TDDR are transferred simultaneously to
the corresponding compare registers when complementary PWM mode is set.
Set TCNT_4 to H'0000 before setting complementary PWM mode.
dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3
must be set to 1/2 the PWM carrier cycle + 1.
Set Value
1/2 PWM carrier cycle + dead time Td
(1/2 PWM carrier cycle + 1 when dead time generation
is disabled by TDER)
Dead time Td (1 when dead time generation is
disabled by TDER)
1/2 PWM carrier cycle
Initial PWM duty value for each phase
H'0000