DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 468

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the
C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control
register (SCSCR) (table 12.14).
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to 16 times the desired bit rate.
(3)
SCI Initialization (Asynchronous Mode):
Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register
(SCSCR), then initialize the SCI as follows.
When changing the operation mode or the communication format, always clear the TE and RE bits
to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1
and initializes the transmit shift register (SCTSR). Clearing the RE bit to 0, however, does not
initialize the RDRF, PER, FER, and ORER flags or receives data register (SCRDR), which retains
their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Rev. 5.00 Mar. 06, 2009 Page 448 of 770
REJ09B0243-0500
Clock
Transmitting and Receiving Data