DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 87

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.5
Selecting division ratios for the frequency divider can change the frequencies of the internal clock
(Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). This is controlled by software
through the frequency control register (FRQCR). The following describes how to specify the
frequencies.
1. In the initial state, IFC2 to IFC0 = H'011 (×1/4), BFC2 to BFC0 = H'011 (×1/4), PFC2 to
2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM.
3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, and MPFC2 to
4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will
PFC0 = H'011 (×1/4), and MPFC2 to MPFC0 = H'011 (×1/4).
MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed at ×8, the
frequencies are determined only be selecting division ratios. When specifying the frequencies,
satisfy the following condition: internal clock (Iφ) ≥ bus clock (Bφ) = peripheral clock (Pφ).
When using the MTU2 clock, specify the frequencies to satisfy the following condition:
internal clock (Iφ) ≥ MTU2 clock (MPφ) ≥ peripheral clock (Pφ).
change after (1 to 24n) cyc + 11Bφ + 7Pφ.
n: Division ratio specified by the BFC bit in FRQCR (1/2, 1/4, or 1/8)
cyc: Clock obtained by dividing EXTAL by 8 with the PLL.
Note: (1 to 24n) depends on the internal state.
Changing Frequency
Rev. 5.00 Mar. 06, 2009 Page 67 of 770
REJ09B0243-0500

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