DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 170

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.4
The on-chip peripheral I/O register is accessed by the bus state controller (BSC) as described in
table 8.2.
Table 8.2
Note: When m = 0 to 3, Bclk:Pclk = 4:1
This LSI adopts synchronous logic, and data of each bus is input and output in synchronization
with the rising edge of the corresponding clock. The L bus access takes one Iclk cycle, I bus
access takes one Bclk cycle, and peripheral bus access takes two Pclk cycles. When the on-chip
peripheral I/O register is accessed by the CPU, the period required for preparation for data transfer
to the I bus is a period of 3 Iclk cycles.
Figure 8.1 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk =
4:1:1. From the L bus, to which the CPU is connected, data is output in synchronization with Iclk.
Since there are four Iclk cycles in a single Bclk cycle when Iclk:Bclk = 4:1, data can be output
onto the L bus in four possible timings within one Bclk cycle. Accordingly, a maximum of four
Iclk cycles of period (four Iclk cycles in the example shown in the figure) is required before the
rising edge of Bclk, on which data is transferred from the L bus to the I bus. Because of this, data
is transferred from the L bus to the I bus in a period of (3 + n) × Iclk (n = 0 to 3) when Iclk:Bclk =
4:1. The relation of the timing of data output to the L bus and the rising edge of Bclk depends on
the state of program execution. In the case shown in figure 8.1, where Bclk = Pclk = 1:1, the
period required for access by the CPU is (3 + n) × Iclk + 1 × Bclk + 2 × Pclk.
Rev. 5.00 Mar. 06, 2009 Page 150 of 770
REJ09B0243-0500
On-chip Peripheral
Module
Connection Bus
Width
Number of
Access
Cycles
When n = 0 to 3, lclk:Bclk = 4:1
When m = 0, 1, Bclk:Pclk = 2:1
When n = 0, 1, lclk:Bclk = 2:1
When m = 0, Bclk:Pclk = 1:1
When n = 0, lclk:Bclk = 1:1
Access to on-chip Peripheral I/O Register
Connection Bus Width of on-chip Peripheral Module and the Number of Access
Cycles
Write (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk
Read (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk + 2 × Iclk
INTC
16
UBC
16
MTU2
16
POE2
16
WDT
16
SCI
8
ADC
16
CMT
16
PFC,
Port
16