DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 430

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4
11.4.1
The WDT can be used to revoke software standby mode with an NMI interrupt or external
interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used
for canceling, so keep the RES pin low until the clock stabilizes.)
1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
3. Transition to software standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting a change in the level input to the NMI or IRQ pin.
5. When the WDT count overflows, the CPG starts supplying the clock and the LSI resumes
11.4.2
While operating in watchdog timer mode, the WDT generates an internal reset of the type
specified by the RSTS bit in WTCSR and asserts a signal through the WDTOVF pin every time
the counter overflows.
1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to prevent the
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, asserts a signal
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the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the
count overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
operation. The WOVF flag in WTCSR is not set when this happens.
clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
counter from overflowing.
through the WDTOVF pin for one cycle of the count clock specified by the CKS2 to CKS0
bits, and generates a reset of the type specified by the RSTS bit. The counter then resumes
counting.
Operation
Canceling Software Standbys
Using Watchdog Timer Mode