DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 162

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(Example 1-3)
• Register specifications
(Example 1-4)
• Register specifications
Rev. 5.00 Mar. 06, 2009 Page 142 of 770
REJ09B0243-0500
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
After an instruction with address H'00037226 is executed, a user break occurs before an
instruction with address H'0003722E is executed.
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,
no user break occurs since instruction fetch is performed for an even address.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008
Specified conditions: Channel A/channel B sequential mode
<Channel A>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
H'00000000, Data mask: H'00000000
H'00027128, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'00031415, Address mask: H'00000000
H'00000000, Data mask: H'00000000
included in the condition)
H'00037226, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'0003722E, Address mask: H'00000000