DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 643

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3.1) Select the on-chip program to be downloaded
(3.2) Set the FEBS parameter necessary for erasure
(3.3) Erasure
(3.4) The return value in the erasing program, FPFR (general register R0) is checked.
(3.5) Determine whether erasure of the necessary blocks has finished.
(3.6) After erasure finishes, clear FKEY and specify software protection.
MOV.L #DLTOP+16,R1
JSR
NOP
A single divided block is erased by one erasing processing. For block divisions, see figure
17.4. To erase two or more blocks, update the erase block number and perform the erasing
processing for each block.
Set the EPVB bit in FECS to 1.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the source select error
detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
The procedures to be carried out after setting FKEY, e.g. download and initialization, are the
same as those in the programming procedure. For details, see the description in section 17.5.2
(2), Programming Procedure in User Program Mode.
Set the erase block number of the user MAT in the flash erase block select parameter (FEBS:
general register R4). If a value other than an erase block number of the user MAT is set, no
block is erased even though the erasing program is executed, and an error is returned to the
return value parameter FPFR.
Similar to as in programming, there is an entry point of the erasing program in the area from
(download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called
and erasing is executed by using the following steps.
⎯ The general registers other than R0 are saved in the erasing program.
⎯ R0 is a return value of the FPFR parameter.
⎯ Since the stack area is used in the erasing program, a stack area of maximum 128 bytes
If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to
(3.5). Blocks that have already been erased can be erased again.
If this LSI is restarted by a power-on reset immediately after user MAT erasing has finished,
secure a reset period (period of RES = 0) that is at least as long as the normal 100 μs.
must be reserved in RAM.
@R1
; Set entry address to R1
; Call erasing routine
Rev. 5.00 Mar. 06, 2009 Page 623 of 770
REJ09B0243-0500