DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 323

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
2. Example of Interrupt Skipping Operation
Figure 9.69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping
count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt
skipping set register (TITCR).
Figure 9.68 Periods during which Interrupt Skipping Count can be Changed
Figure 9.67 Example of Interrupt Skipping Operation Setting Procedure
changing skipping count
Period during which
Clear interrupt skipping counter
can be performed
enable interrupt skipping
Set skipping count and
TCNT_3
<Interrupt skipping>
Interrupt skipping
TCNT_4
changing skipping count
Period during which
can be performed
[1]
[2]
[1] Set bits T3AEN and T4VEN in the timer interrupt
[2] Specify the interrupt skipping count within the
Note: The setting of TITCR must be done while the
skipping set register (TITCR) to 0 to clear the
skipping counter.
range from 0 to 7 times in bits 3ACOR2 to
3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and
enable interrupt skipping through bits T3AEN and
T4VEN.
Before changing the skipping count, be sure to
changing skipping count
TGIA_3 and TCIV_4 interrupt requests are
disabled by the settings of registers TIER_3
and TIER_4 along with under the conditions in
which TGFA_3 and TCFV_4 flag settings by
compare match never occur.
clear the T3AEN and T4VEN bits to 0 to clear
the skipping counter.
Period during which
can be performed
Rev. 5.00 Mar. 06, 2009 Page 303 of 770
changing skipping count
Period during which
can be performed
REJ09B0243-0500

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