DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 515

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.4.5
The A/D converter can be independently activated by an A/D conversion request from the interval
timer of the MTU2.
To activate the A/D converter by the MTU2, first set the TRGE bit in the A/D control/status
register (ADCSR) to 1, and then set the A/D trigger select register (ADTSR). After this register
setting has been made, the ADST bit in ADCR is automatically set to 1 when an A/D conversion
request from the interval timer of the MTU2 occurs. The timing from setting of the ADST bit until
the start of A/D conversion is the same as when 1 is written to the ADST bit by software.
13.4.6
A/D conversion can be externally triggered. When the TRGE bit in the A/D control/status register
(ADCSR) is set to 1 while the TRGS3 to TRGS0 bits in the A/D trigger select register_0
(ADTSR_0) is set to external trigger input, external trigger input is enabled at the ADTRG pin. A
falling edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other
operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by
software. Figure 13.3 shows the timing.
CK
ADTRG
External trigger
signal
ADST
A/D Converter Activation by MTU2
External Trigger Input Timing
Figure 13.3 External Trigger Input Timing
Rev. 5.00 Mar. 06, 2009 Page 495 of 770
A/D conversion
REJ09B0243-0500

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