DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 481

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Receiving Serial Data (Clock Synchronous Mode): Figure 12.12 shows a sample flowchart for
receiving serial data. Use the following procedure for serial data reception after enabling the SCIF
for reception.
When switching from asynchronous mode to clock synchronous mode, make sure that the ORER,
PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not
be set and data reception cannot be started.
No
No
Read receive data in SCRDR,
Figure 12.12 Sample Flowchart for Receiving Serial Data (1)
Read ORER flag in SCSSR
Read RDRF flag in SCSSR
Clear RE bit in SCSCR to 0
and clear RDRF flag
All data received?
Start of reception
End of reception
in SCSSR to 0
ORER = 1?
RDRF = 1?
No
Yes
Yes
Error handling
Yes
[1] Receive error handling:
[2] SCI status check and receive data read:
[3] Serial reception continuation procedure:
identify any error, perform the appropriate
error handling, then clear the ORER flag
to 0. Reception cannot be resumed while
the ORER flag is set to 1.
then read the receive data in SCRDR,
and clear the RDRF flag to 0. The
transition of the RDRF flag from 0 to 1
can also be identified by an RXI interrupt.
receive data register (SCRDR) and clear
the RDRF flag to 0 before the MSB (bit 7)
of the current frame is received.
Read the ORER flag in SCSSR to
Read SCSSR and check that RDRF = 1,
To continue serial reception, read the
Rev. 5.00 Mar. 06, 2009 Page 461 of 770
REJ09B0243-0500

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