DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 188
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 9.10 TPSC1 and TPSC0 (Channel 5)
Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value
9.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Rev. 5.00 Mar. 06, 2009 Page 168 of 770
REJ09B0243-0500
Channel
5
Bit
7
6
should always be 0.
Bit Name
—
BFE
Timer Mode Register (TMDR)
Bit 1
TPSC1
0
1
Initial value:
Initial
Value
0
0
Bit 0
TPSC0
0
1
0
1
R/W:
Bit:
7
0
-
-
R/W
—
R/W
Description
Internal clock: counts on MPφ/1
Internal clock: counts on MPφ/4
Internal clock: counts on MPφ/16
Internal clock: counts on MPφ/64
R/W
BFE
6
0
Description
This bit is always read as 0. The write value should
always be 0.
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
When TGRF is used as a buffer register, TGRF
compare match is generated.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
Reserved
Buffer Operation E
R/W
BFB
5
0
operation
R/W
BFA
4
0
R/W
3
0
R/W
2
0
MD[3:0]
R/W
1
0
R/W
0
0
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