DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 151

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
12
11
10
9, 8
7
6
Bit Name
SCMFDB
PCTE
PCBA
DBEA
PCBB
Initial
Value
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
0: Disables PC trace
1: Enables PC trace
Selects the break timing of the instruction fetch cycle
for channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
1: PC break of channel A is set after instruction
Selects whether or not the data bus condition is
included in the break condition of channel A.
0: No data bus condition is included in the condition of
1: The data bus condition is included in the condition of
Selects the break timing of the instruction fetch cycle
for channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
1: PC break of channel B is set after instruction
I Bus Cycle Condition Match Flag B
When the I bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel B does not
1: The I bus cycle condition for channel B matches
PC Trace Enable
PC Break Select A
Reserved
These bits are always read as 0. The write value
should always be 0.
Data Break Enable A
PC Break Select B
channel A
channel A
execution
execution
match
execution
execution
Rev. 5.00 Mar. 06, 2009 Page 131 of 770
REJ09B0243-0500

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