DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 398

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and
Operation is Restarted in Normal Mode: Figure 9.149 shows an explanatory diagram of the
case where an error occurs in reset-synchronized PWM mode and operation is restarted in normal
mode after re-setting.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized
11. Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.)
12. Initialize the pins with TIOR.
13. Set MTU2 output with the PFC.
14. Operation is restarted by TSTR.
Rev. 5.00 Mar. 06, 2009 Page 378 of 770
REJ09B0243-0500
MTU2 module output
After a reset, MTU2 output is low and ports are in the high-impedance state.
Select the reset-synchronized PWM output level and cyclic output enabling/disabling with
TOCR.
Set reset-synchronized PWM.
Enable channel 3 and 4 output with TOER.
Set MTU2 output with the PFC.
The count operation is started by TSTR.
The reset-synchronized PWM waveform is output on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
PWM output initial value.)
Port output
TIOC3D
TIOC3A
TIOC3B
Figure 9.149 Error Occurrence in Reset-Synchronized PWM Mode,
PE11
PE8
PE9
RESET
1
TOCR
2
High-Z
High-Z
High-Z
(RPWM)
TMDR
3
Recovery in Normal Mode
TOER
(1)
4
(MTU2)
PFC
5
TSTR
(1)
6
Match
7
occurs
Error
8
(PORT)
PFC
9
TSTR
(0)
10
(normal)
TMDR
11
0 out)
(1 init
TIOR
12
(MTU2)
PFC
13
TSTR
(1)
14

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