DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 408

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 5.00 Mar. 06, 2009 Page 388 of 770
REJ09B0243-0500
Bit
13
12
11 to 9 ⎯
Bit Name
POE1F
POE0F
Initial
value
0
0
All 0
R/W
R/(W)*
R/(W)*
R
1
1
Description
POE1 Flag
This flag indicates that a high impedance request has
been input to the POE1 pin.
[Clearing conditions]
[Setting condition]
POE0 Flag
This flag indicates that a high impedance request has
been input to the POE0 pin.
[Clearing conditions]
[Setting condition]
Reserved
These bits are always read as 0. The write value should
always be 0.
By writing 0 to POE1F after reading POE1F = 1
(when the falling edge is selected by bits 3 and 2 in
ICSR1)
By writing 0 to POE1F after reading POE1F = 1 after
a high level input to POE1 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 3 and 2 in ICSR1)
When the input set by ICSR1 bits 3 and 2 occurs at
the POE1 pin
By writing 0 to POE0F after reading POE0F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR1)
By writing 0 to POE0F after reading POE0F = 1 after
a high level input to POE0 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR1)
When the input set by ICSR1 bits 1 and 0 occurs at
the POE0 pin

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