DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 126

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Interrupt Controller (INTC)
6.5
Interrupt Exception Handling Vector Table
Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt
priorities.
Individual interrupt sources are allocated to different vector numbers and vector table address
offsets. Vector table addresses are calculated from the vector numbers and vector table address
offsets. For interrupt exception handling, the start address of the exception handling routine is
fetched from the vector table address in the vector table. For the details on calculation of vector
table addresses, see table 5.4 in section 5, Exception Handling.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0
and 15 for each pin or module by setting interrupt priority registers A to F and H to M (IPRA to
IPRF and IPRH to IPRM). However, when interrupt sources whose priority levels are allocated
with the same IPR are requested, the interrupt of the smaller vector number has priority. This
priority cannot be changed. Priority levels of IRQ interrupts and on-chip peripheral module
interrupts are initialized to level 0 at a power-on reset. If the same priority level is allocated to two
or more interrupt sources and interrupts from those sources occur simultaneously, they are
processed by the default priority order shown in table 6.3.
Rev. 5.00 Mar. 06, 2009 Page 106 of 770
REJ09B0243-0500