DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 133

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 6.4
Notes: * In the case that m1 = m2 = m3 = m4 = 1 × Icyc.
Item
Interrupt priority decision
and comparison with mask
bits in SR
Wait for completion of
sequence currently being
executed by CPU
Time from start of interrupt
exception handling until
fetch of first instruction of
exception handling routine
starts
Interrupt
response
time
m1 to m4 are the number of cycles needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Interrupt Response Time
Minimum*:
Maximum:
Total:
NMI
1 × Icyc + 2 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 2 ×
Pcyc + m1 + m2
+ m3 + X
12 × Icyc +
2 × Pcyc
16 × Icyc +
2 × Pcyc + 2 ×
(m1 + m2 + m3)
+ m4
Number of Cycles
IRQ
1 × Icyc + 1 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 1 ×
Pcyc + m1 + m2
+ m3 + X
12 × Icyc +
1 × Pcyc
16 × Icyc +
1 × Pcyc + 2
(m1 + m2 + m3)
+ m4
Peripheral
Modules
1 × Icyc + 2 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 2 ×
Pcyc + m1 + m2
+ m3 + X
12 × Icyc +
2 × Pcyc
16 × Icyc +
2 × Pcyc + 2
(m1 + m2 + m3)
+ m4
Rev. 5.00 Mar. 06, 2009 Page 113 of 770
Remarks
The longest sequence is
for interrupt or address-
error exception handling
(X = 7 × Icyc + m1 + m2
+ m3 + m4). If an
interrupt-masking
instruction follows,
however, the time may
be even longer.
Performs the saving PC
and SR, and vector
address fetch.
SR, PC, and vector table
are all in on-chip RAM.
REJ09B0243-0500