DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 129
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 129 of 794
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6.6
6.6.1
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt from interrupt requests sent,
3. The interrupt controller compares the priority level of the selected interrupt request with the
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR.
8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high
9. The CPU reads the start address of the exception handling routine from the exception vector
according to the priority levels set in interrupt priority registers A to F and H to M (IPRA to
IPRF and IPRH to IPRM). Interrupts that have lower-priority than that of the selected interrupt
are ignored*. If interrupts that have the same priority level or interrupts within a same module
occur simultaneously, the interrupt with the highest priority is selected according to the default
priority shown in table 6.3.
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the
selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If
the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt
controller accepts the request and sends an interrupt request signal to the CPU.
an instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception handling.
level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high
level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception
processing instead of instruction execution as noted in 5. above. However, if the interrupt
controller accepts an interrupt with a higher priority than the interrupt just to be accepted, the
IRQOUT pin holds low level.
table for the accepted interrupt, branches to that address, and starts executing the program.
This branch is not a delayed branch.
Interrupt Operation
Interrupt Sequence
Rev. 5.00 Mar. 06, 2009 Page 109 of 770
REJ09B0243-0500
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