DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 149

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.2.11
BRCR sets the following conditions:
1. Channels A and B are used in two independent channel conditions or under the sequential
2. A break is set before or after instruction execution.
3. Specify whether to include the number of execution times on channel B in comparison
4. Determine whether to include data bus on channels A and B in comparison conditions.
5. Enable PC trace.
6. Specify whether to request the user break interrupt when channels A and B match with
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Initial value:
Initial value:
Bit
31 to 20 ⎯
19
condition.
conditions.
comparison conditions.
R/W:
R/W:
Bit:
Bit:
SCM
R/W
Break Control Register (BRCR)
FCA
31
15
R
Bit Name
UBIDB
0
0
-
SCM
R/W
FCB
30
14
R
0
0
-
SCM
R/W
FDA
29
13
R
0
0
-
Initial
Value
All 0
0
SCM
R/W
FDB
28
12
R
0
0
-
PCTE
R/W
27
11
R
0
0
-
R/W
R
R/W
PCBA
R/W
26
10
R
0
0
-
Description
Enables or disables the user break interrupt request
when the channel B break conditions are satisfied.
0: User break interrupt request is enabled when break
1: User break interrupt request is disabled when break
Reserved
These bits are always read as 0. The write value
should always be 0.
User Break Disable B
25
R
R
0
9
0
-
-
conditions are satisfied
conditions are satisfied
24
R
R
0
8
0
-
-
DBEA
R/W
23
R
0
7
0
-
PCBB
R/W
22
Rev. 5.00 Mar. 06, 2009 Page 129 of 770
R
0
6
0
-
DBEB
R/W
21
R
0
5
0
-
20
R
R
0
4
0
-
-
UBIDB
R/W
R/W
SEQ
19
0
3
0
REJ09B0243-0500
18
R
R
0
2
0
-
-
UBIDA
R/W
17
R
0
1
0
-
ETBE
R/W
16
R
0
0
0
-