DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 495

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Equation 1:
Where: M: Receive margin (%)
Equation 2:
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
When D = 0.5 and F = 0:
M
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Synchronization
sampling timing
Data sampling
Receive data
M = (0.5 -
Base clock
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
= (0.5 – 1/(2 × 16)) × 100%
= 46.875%
Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode
(RXD)
timing
2N
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
1
) - (L - 0.5) F -
Start bit
8 clocks
16 clocks
–7.5 clocks
D - 0.5
N
(1+F) × 100 %
+7.5 clocks
Rev. 5.00 Mar. 06, 2009 Page 475 of 770
D0
REJ09B0243-0500
D1