DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 494

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.7.3
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set
and the parity error flag (PER) may also be set. Note that, although transfer of received data to
SCRDR is halted in the break state, the SCI receiver continues to operate.
12.7.4
The I/O condition and level of the TXD pin are determined by the SPB0DT bit in the serial port
register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During
the period, mark status is performed by SPB0DT bit. Therefore, the SPB0DT bit should be set to 1
at first (high level output).
To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear
the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized
regardless of the current transmission state, and 0 is output from the TXD pin.
12.7.5
The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous
mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples
on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The
timing is shown in figure 12.21.
Rev. 5.00 Mar. 06, 2009 Page 474 of 770
REJ09B0243-0500
Break Detection and Processing
Sending a Break Signal
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)