DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 528

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 5.00 Mar. 06, 2009 Page 508 of 770
REJ09B0243-0500
Bit
15 to 8
7
6
5 to 2
1, 0
2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the
Bit Name
CMF
CMIE
CKS[1:0]
flag will not be cleared by simply writing 0 to it. In this case, read the bit as 1 once again
and write 0 to it.
Initial
value
All 0
0
0
All 0
00
R/W
R
R/(W)*
R/W
R
R/W
1
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing condition]
[Setting condition]
1: CMCNT and CMCOR values match
Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF=1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Clock Select 1 and 0
Select the clock to be input to CMCNT from four internal
clocks obtained by dividing the peripheral operating
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
When 0 is written to this bit after reading CMF = 1*
2

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