DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 412

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 5.00 Mar. 06, 2009 Page 392 of 770
REJ09B0243-0500
Bit
15 to 13 —
12
11, 10
9
8
Bit Name
POE8F
POE8E
PIE3
0
0
Initial
value
0
All 0
All 0
R/W
R
R/(W)*
R
R/W*
R/W
2
1
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
POE8 Flag
This flag indicates that a high impedance request has
been input to the POE8 pin.
[Clearing conditions]
[Setting condition]
Reserved
These bits are always read as 0. The write value should
always be 0.
POE8 High-Impedance Enable
This bit specifies whether to place the pins in high-
impedance state when the POE8F bit in ICSR3 is set
to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
Port Interrupt Enable 3
(Supported only by the SH7125. Write 0 to this bit in the
SH7124.)
This bit enables or disables interrupt requests when the
POE8 bit in ICSR3 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
By writing 0 to POE8F after reading POE8F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR3)·
By writing 0 to POE8F after reading POE8F = 1 after
a high level input to POE8 is sampled at Pf/8, Pf/16,
or Pf/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR3)
When the input condition set by bits 1 and 0 in
ICSR3 occurs at the POE8 pin

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