HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1010

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 27
27.7.2
Generation of an interrupt or activation of the DMAC upon the end of A/D conversion is only
allowed once per end of A/D conversion.
The conditions for the end of A/D conversion are the same as the setting conditions of the ADF bit
of ADCSR.
According to the table below, A/D conversion value should be transferred by DMA transfer (in
cycle steal mode), with the corresponding conversion mode and number of channels for
conversion.
27.7.3
For the analog input design of this LSI, conversion accuracy is guaranteed for an input signal with
signal-source impedance of 5 kΩ or less. The specification is for charging input capacitance of the
sample and hold circuit of the A/D converter within sampling time. When the output impedance of
the sensor exceeds 5 kΩ, conversion accuracy is not guaranteed due to insufficient charging. If
large external capacitance is set at conversion in single mode, signal-source impedance is ignored
since input load is only internal input resistance of 3 kΩ. However, an analog signal with large
differential coefficient (5 mV/µs or greater) cannot be followed up because of a low-pass filter
(figure 27.8). When converting high-speed analog signals or converting in scan mode, insert a
low-impedance buffer.
Rev. 3.00
REJ09B0033-0300
Conversion Mode
Single mode
Multi mode or
Scan mode
Notes on A/D Conversion-End Interrupt and DMA Transfer
Allowable Signal-Source Impedance
Jan. 18, 2008
A/D Converter
Number of Channels
for Conversion
1
1
2
3
4
Page 948 of 1458
Data Size
1 word
1 word
2 words
3 words
4 words
Transfer Size for DMAC
Word
Word
Longword
16 bytes
16 bytes