HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 138

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
Notes:
Rev. 3.00 Jan. 18, 2008 Page 76 of 1458
REJ09B0033-0300
Instruction
STC
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STS
STS
STS
STS.L
STS.L
STS.L
TRAPA #imm
R7_BANK,Rn
SR,@–Rn
GBR,@–Rn
VBR,@–Rn
SSR,@–Rn
SPC,@–Rn
MACH,Rn
MACL,Rn
PR,Rn
MACH,@–Rn
MACL,@–Rn
PR,@–Rn
R0_BANK,@–Rn
R1_BANK,@–Rn
R2_BANK,@–Rn
R3_BANK,@–Rn
R4_BANK,@–Rn
R5_BANK,@–Rn
R6_BANK,@–Rn
R7_BANK,@–Rn
CPU
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased in the following conditions.
a. If there is a conflict between an instruction fetch and a data access
b. If the destination register of a load instruction (memory → register) is also used by
For addressing modes with displacement (disp) as shown below, the assembler
description in this manual indicates the value before it is scaled (x 1, x 2, or x 4)
according to the operand size to clarify the LSI operation. For details on assembler
description, refer to the description rules in each assembler.
the following instruction.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp:12 ; PC relative
Instruction
Code
0000nnnn11110010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
R7_BANK→Rn
Rn–4→Rn, SR→(Rn)
Rn–4→Rn, GBR→(Rn)
Rn–4→Rn, VBR→(Rn)
Rn–4→Rn, SSR→(Rn)
Rn–4→Rn, SPC→(Rn)
Rn–4→Rn, R0_BANK→(Rn)
Rn–4→Rn, R1_BANK→(Rn)
Rn–4→Rn, R2_BANK→(Rn)
Rn–4→Rn, R3_BANK→(Rn)
Rn–4→Rn, R4_BANK→(Rn)
Rn–4→Rn, R5_BANK→(Rn)
Rn–4→Rn, R6_BANK→(Rn)
Rn–4→Rn, R7_BANK→(Rn)
MACH→Rn
MACL→Rn
PR→Rn
Rn–4→Rn, MACH→(Rn)
Rn–4→Rn, MACL→(Rn)
Rn–4→Rn, PR→(Rn)
Unconditional trap exception
occurs*
2
Privileged
Mode
√
√
–
√
√
√
√
√
√
√
√
√
√
√
–
–
–
–
–
–
–
Cycles T Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–