HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 110

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
2.3.4
The control registers (SR, SSR, SPC, GBR, and VBR) can be accessed by the LDC or STC
instruction in privileged mode. The GBR register can be accessed in the user mode.
The control registers are described below.
(1)
The status register (SR) indicates the system status as shown below. The SR register can be
accessed only in privileged mode.
Rev. 3.00 Jan. 18, 2008 Page 48 of 1458
REJ09B0033-0300
Bit
31
30
29
Status Register (SR)
Control Registers
CPU
Bit Name

MD
RB
Initial
Value
0
1
1
R/W
R
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Processing Mode
Indicates the CPU processing mode.
0: User mode
1: Privileged mode
The MD bit is set to 1 in reset or exception handling
state.
Register Bank
The general registers R0 to R7 are banked registers.
0: In this case, R0_BANK0 to R7_BANK0 and R8 to
1: In this case, R0_BANK1 to R7_BANK1 and R8 to
The RB bit is set to 1 in reset or exception handling
state.
R15 are used as general registers.
R0_BANK1 to R7_BANK1 can be accessed by the
LDC or STR instruction.
R15 are used as general registers.
R0_BANK0 to R7_BANK0 can be accessed by the
LDC or STR instruction.