HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1151

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• After read sequence, FIFO includes data. If necessary, 100 is written to the SET2 to SET0 bits
• The end of the transfer with the DMAC is confirmed, and 0 is set to the DMAEN bit in
• When the CRC error (CRCERI) or the command timeout error (CTERI) occurs during
• When the CRC error (CRCERI) or the data timeout error (DTERI) occurs during read data
Notes: 1. Access from the DMAC the FIFO should be performed by byte or longword data.
in DMACR to read every data in FIFO.
DMACR.
command response reception, write 1 to the CMDOFF bit and set DMACR to H'00.
reception, write 1 to the CMDOFF bit and set DMACR to H'00 to clear the FIFO.
2. In multiblock transfer, no normal command response can be received if you terminate
the command sequence (by writing 1 in the CMDOFF bit) before the command
response end interrupt (CRPI). To receive a normal command response, you need to
continue the command sequence (by setting the RD_CONTI bit to 1) until the
reception of the command response is completed.
Section 31
Rev. 3.00 Jan. 18, 2008 Page 1089 of 1458
MultiMediaCard Interface (MMCIF)
REJ09B0033-0300