HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 158

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 3 DSP Operating Unit
Table 3.7
(3)
(a)
The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In
addition, note that at least one instruction is required between the SETRC instruction and a repeat
start instruction.
(b) Illegal instruction one or more instructions following the repeat detection instruction
If one of the following instructions is executed between an instruction following a repeat detection
instruction to a repeat end instruction, an illegal instruction exception occurs.
• Branch instructions
• Repeat control instructions
• Load instructions for SR, RS, and RE registers
Note: This restriction applies to all instructions for a repeat loop consisting of one to three
Rev. 3.00 Jan. 18, 2008 Page 96 of 1458
REJ09B0033-0300
Instruction
STC RS, Rn
STC RE, Rn
STC.L RS, @-Rn
STC.L RE, @-Rn
LDC.L @Rn+, RS
LDC.L @Rn+, RE
LDC Rn,RS
LDC Rn, RE
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Restrictions on Repeat Loop Control
Repeat control instruction assignment
instructions and to three instructions including a repeat end instruction.
DSP Mode Extended System Control Instructions
Operation
RS→Rn
RE→Rn
Rn-4→Rn, RS→(Rn)
Rn-4→Rn, RE→(Rn)
(Rn)→RS, Rn+4→Rn
(Rn)→RE, Rn+4→Rn
Rn →RS
Rn→RE
Number of
Execution States
1
1
1
1
4
4
4
4

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