HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 329

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt
handling. IRQ interrupts specified for edge detection can be used to recover from a standby state
when the corresponding interrupt level is higher than that set in the I3 to I0 bits of the SR register.
(However, when RTC is used, recovering from standby by using the clock for RTC is enabled.)
8.4.3
IRL interrupts are input by pins IRL3 to IRL0 as level. The priority level is the higher level that is
indicated by IRL3 to IRL0 pins. When the values of IRL3 to IRL0 pins are 0 (B'0000), it indicates
the highest level interrupt request (interrupt priority level 15). When the values of the pins are 15
(B'1111), no interrupt is requested (interrupt priority level 0). Figure 8.2 shows an example of
connection for IRL interrupt.
IRL interrupts are included with noise canceller function and detected when the sampled levels of
each peripheral module clock keep same value for 2 cycles. This prevents sampling error level in
IRL pin changing.
IRL interrupts priority level should be kept until interrupt is accepted and its handling is started.
However, changing to higher level is enabled.
The interrupt mask bits I3 to I0 in the status register (SR) are not affected by the IRL interrupt
handling.
Interrupt
request
IRL interrupts
Figure 8.2
encoder
Example of IRL Interrupt Connection
Priority
IRL3 to IRL0
4
Rev. 3.00 Jan. 18, 2008 Page 267 of 1458
Section 8
SH7720 / SH7721 Group
IRL3 to IRL0
Interrupt Controller (INTC)
REJ09B0033-0300