HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 291

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(3)
• Conditions
• Types
• Save address
• Exception code
• Remarks
(4)
• Conditions
• Types
• Save address
• Exception code
• Remarks
 When undefined code in a delay slot is decoded
 When a privileged instruction in a delay slot is decoded in user mode
 When an instruction that rewrites PC in a delay slot is decoded
Instruction synchronous, re-execution type
A delayed branch instruction address
H'1A0
None
TRAPA instruction executed
Instruction synchronous, processing-completion type
An address of an instruction following TRAPA
H'160
The exception is a processing-completion type, so an instruction after the TRAPA instruction
is saved to SPC. The 8-bit immediate value in the TRAPA instruction is set in TRA[9:2].
Illegal slot instruction
Unconditional trap
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
Rev. 3.00 Jan. 18, 2008 Page 229 of 1458
Section 7 Exception Handling
REJ09B0033-0300