HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 687

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.4.4
In synchronous serial communication, data on the communication line is output from a falling
edge of the serial clock to the next falling edge. Data is guaranteed valid at the rising edge of the
serial clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the MSB.
In synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial
clock.
(1)
A fixed 8-bit data format is used. No parity or multiprocessor bits are added.
(2)
An internal clock generated by the on-chip baud rate generator or an external clock input through
the SCK pin can be selected as the serial clock for the SCIF, according to the setting of the CKE1
and CKE0 bits in SCSCR.
Eight serial clock pulses are output in the transfer of one character, and when no
transmission/reception is performed, the clock is fixed high. However, when the operation mode is
reception only, the synchronous clock output continues while the RE bit is set to 1. To fix the
clock high every time one character is transferred, write to the transmit FIFO data register
(SCFTDR) the same number of dummy data bytes as the data bytes to be received and set the TE
and RE bits to 1 at the same time to transmit the dummy data. When the specified number of data
bytes are transmitted, the clock is fixed high.
When the external clock is selected:
The SCIF operates on the external clock input through the SCK pin.
Serial clock
Serial data
Data Transfer Format
Clock
Serial Operation in Synchronous Mode
don't care
*
Figure 18.12
Note: * High in continuous transmission/reception
LSB
Bit 0
Bit 1
Data Format in Synchronous Communication
One unit of transfer data (character or frame)
Bit 2
Section 18
Bit 3
Serial Communication Interface with FIFO (SCIF)
Bit 4
Rev. 3.00 Jan. 18, 2008 Page 625 of 1458
Bit 5
Bit 6
Bit 7
MSB
REJ09B0033-0300
don't care
*