HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 724

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
(Master output)
Rev. 3.00 Jan. 18, 2008 Page 662 of 1458
REJ09B0033-0300
(Master output)
(Slave output)
processing
ICDRS
ICDRT
TDRE
TEND
User
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
SDA
SDA
SCL
[2] Instruction of start
I
2
C Bus Interface (IIC)
condition issuance
Figure 20.5
Bit 7
1
[3] Write data to ICDRT (first byte)
Bit 6
2
Address + R/W
Master Transmit Mode Operation Timing (1)
Bit 5
3
Address + R/W
Slave address
Bit 4
4
Bit 3
5
Bit 2
6
[4] Write data to ICDRT (second byte)
Bit 1
7
R/W
Bit 0
8
A
9
[5] Write data to ICDRT (third byte)
Data 1
Data 1
Bit 7
1
Bit 6
Data 2
2