HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 777

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.4.4
(1)
Writing and reading of transmit/receive data are performed for the following registers.
• Transmit data writing: SITDR (32-bit access)
• Receive data reading: SIRDR (32-bit access)
Figure 21.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in
Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR.
Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR.
To achieve left and right same audio output while stereo is specified for transmit data, specify the
TLREP bit in SITDAR. Tables 21.6 and 21.7 show the audio mode specification for transmit data
and that for receive data, respectively.
Transmit/Receive Data
unshaded areas is not transmitted or received.
Register Allocation of Transfer Data
(a) 16-bit stereo data
(b) 16-bit monaural data
(c) 8-bit monaural data
(d) 16-bit stereo data (left and right same audio output) data
Figure 21.5
31
31
31
31
Data
L-channel data
24 23
24 23
24 23
24 23
Data
Data
Transmit/Receive Data Bit Alignment
16 15
16 15
16 15
16 15
Rev. 3.00 Jan. 18, 2008 Page 715 of 1458
R-channel data
Section 21
8 7
8 7
8 7
8 7
Serial I/O with FIFO (SIOF)
0
0
0
0
REJ09B0033-0300