HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 784

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21
(2)
Figure 21.10 shows an example of settings and operation for master mode reception.
Rev. 3.00 Jan. 18, 2008 Page 722 of 1458
REJ09B0033-0300
Reception in Master Mode
Serial I/O with FIFO (SIOF)
10
11
12
No.
1
2
3
4
5
6
7
8
9
Figure 21.10
Store SIOFRXD receive data in SIRDR
SIRDAR, SICDAR, and SIFCTR
Clear the RXE bit in SICTR to 0
Set the MSSEL bit in SISCR to 1
Set the SCKE bit in SICTR to 1
Reset the master clock source
Set SIMDR, SISCR, SITDAR,
Set the FSE bit in SICTR to 0
and BPRS=00000 in SISCR
synchronously with SIOFSYNC
Set the FSE and RXE bits
Start the setting FSE=0,
to the RXRST in SISCR
and baud rate in SISCR
Start SIOFSCK output
Add pulse (0→1→0)
TXE=0 and other bit.
Transfer ended?
Set BRDV=111
in SICTR to 1
Read SIRDR
RDREQ = 1?
transmit mode?
Flow Chart
Change other
Start
Yes
Yes
Yes
Example of Receive Operation in Master Mode
No
No
No
End
Set the start for frame
synchronous signal output and
enable reception
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set operation start for
baud rate generator
Read receive data
Set to disable reception
Synchronize this LSI internal
frame with FSE=0 if restarting
recept later.
Execute internal initialization
of the bit rate generator
if restarting recept later.
'No' requires further setting
if transmission is not restarted
(No).
When returning to the same
recept mode from here,
go back to No.4, FSE setting,
on this flowchart.
Go to "Start" on each flowchart.
SIOF Settings
Output serial clock
Output frame
synchronous signal
Issue receive transfer
request according to the
receive FIFO threshold
value
End reception
Reception
SIOF Operation