HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 615

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
16.2.3
CMCNT is a 32-bit register that is used as an up-counter.
A counter operation is set by the compare match timer control/status register (CMCSR).
Therefore, set CMCSR first, before starting a channel operation corresponding to the compare
match timer start register (CMSTR). When the 16-bit counter operation is selected by the CMS
bit, bits 15 to 0 of this register become valid. When the register should be written to, write the data
that is added H'0000 to the upper half in a 32-bit operation. The contents of this register are
initialized to H'00000000.
16.2.4
CMCOR is a 32-bit register that sets the compare match period with CMCNT for each channel.
When the 16-bit counter operation is selected by the CMS bit in CMCSR, bits 15 to 0 of this
register become valid. When the register should be written to, write the data that is added H'0000
to the upper half in a 32-bit operation.
An overflow is detected when CMCNT is cleared to 0 and this register is H'FFFFFFFF. The
contents of this register are initialized to H'FFFFFFFF.
Bit
2
1
0
*
Bit Name
CKS2
CKS1
CKS0
Compare Match Timer Counter (CMCNT)
Compare Match Timer Constant Register (CMCOR)
Only 0 can be written to clear the flag.
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Clock Select 2 to 0
These bits select the clock input to CMCNT. When the
STRn (n: 4 to 0) bit in CMSTR is set to 1, CMCNT begins
incrementing with the clock selected by these bits.
000: Pφ/8
001: Pφ/32
010: Pφ/128
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Rev. 3.00 Jan. 18, 2008 Page 553 of 1458
Section 16 Compare Match Timer (CMT)
REJ09B0033-0300