HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 803

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Each interrupt mask flag is able to prohibit interrupt generation of each interrupt that indicated in
interrupt status flag. Every mask bits are automatically set when TE or RE bit are modified to 1.
TFEM and THEM are 1 when TE = 0. RFFM and RHFM are 1 when RE = 0. Each mask bit is
reset as 1.
Bit
15 to 12 
11
10
9
8
7 to 4
3
Bit Name
TFEM
RFFM
THEM
RHFM

TFE
Initial Value
All 0
1
1
1
1
All 0
1
R/W
R
R/W
R/W
R/W
R/W
R
R
Description
Reserved
These bits are always read as 0. The write
value should always be 0.
Transmit FIFO Empty Interrupt Mask
0: TFE Interrupt enable
1: TFE interrupt masked
Receive FIFO Full Interrupt Mask
0: RFF Interrupt enable
1: RFF Interrupt masked
Threshold of Transmit FIFO Empty Interrupt
Mask
0: THE Interrupt enable
1: THE Interrupt masked
Threshold of Receive FIFO Full Interrupt Mask
0: RHF Interrupt enable
1: RHF Interrupt masked
Reserved
These bits are always read as 0. The write
value should always be 0.
Transmit FIFO Empty Interrupt
0: Normal state
[Clearing condition]
•
1: TxFIFO empty interrupt
[Setting conditions]
•
•
•
Data are written into FIFO
Reset
No effective data in area of FIFO
TE bit (ACTR1) is set to 0 (TFEM bit is set
to 1)
Section 22
Rev. 3.00 Jan. 18, 2008 Page 741 of 1458
Analog Front End Interface (AFEIF)
REJ09B0033-0300