HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 696

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18
Rev. 3.00 Jan. 18, 2008 Page 634 of 1458
REJ09B0033-0300
Figure 18.16
Serial Communication Interface with FIFO (SCIF)
and RTRG0 in SCFCR, and set transmit
Set receive trigger number in RTRG1
trigger number in TTRG1 and TTRG0
Clear TE and RE bits in SCSCR to 0
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data
interrupt, set TIE bit to 1
When using receive FIFO data
interrupt, set RIE bit to 1
Read TDFE and RDF bits in SCSSR
SCSSR after reading 1 from them
receive data bytes from SCFRDR
Clear TFRST and RFRST bits in
Write 0 to TDFE and RDF bits in
Write transmit data to SCFTDR
Read receive trigger number of
Set TFRST and RFRST bits in
Sample Simultaneous Serial Transmission and Reception Flowchart (2)
transmission/reception
transmission/reception
1-bit interval elapsed?
Start of simultaneous
SCFCR to 1
SCFCR to 0
TDFE =1?
TDFE =1?
RDF =1?
Yes
RDF =1?
End of
Yes
(Second and Subsequent Transfer)
Yes
Wait
No
No
No
1
2
3
4
5
6
1. Set the receive trigger number and
2. Reset the receive FIFO and transmit
3. Write transmit data to SCFTDR, and
4. Wait for one bit interval.
5. Transmission/reception is started when
6. After the end of transmission/reception,
transmit trigger number in SCFCR.
FIFO.
if there is receive data in the FIFO,
read receive data until there is less
than the receive trigger setting number,
read the TDFE and RDF bits in SCSSR,
and if 1, clear to 0.
the TE and RE bits in SCSCR are set
to 1. The TE and RE bits must be set
simultaneously.
clear the TE and RE bits to 0.