HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 780

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21
(2)
The CODEC normally outputs the SIOFSYNC signal as synchronization pulse (FS). In this
method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame
time has been passed (not the normal FS output timing) to transmit or receive control data. This
method is valid for SIOF slave mode. The following summarizes the control data interface
procedure by the secondary FS.
• Transmit normal transmit data of LSB = 0 (the SIOF forcibly clears 0).
• To execute control data transmission, send transmit data of LSB = 1 (the SIOF forcibly set to 1
• The CODEC outputs the secondary FS.
• The SIOF transmits or receives (stores in SIRCDR) control data (data specified by SITCDR)
Figure 21.8 shows an example of the control data interface timing by the secondary FS.
Rev. 3.00 Jan. 18, 2008 Page 718 of 1458
REJ09B0033-0300
SIOFRxD
SIOFSCK
SIOFSYNC
SIOFTxD
by writing SITCDR).
synchronously with the secondary FS.
Control by Secondary FS (Slave Mode 2)
Serial I/O with FIFO (SIOF)
Specifications: TRMD[1:0]=01,
Normal FS
L-channel
No.0
data
Slot
Figure 21.8
TDLE=1,
RDLE=1,
CD0E=1,
LSB=1 (Secondary FS request)
1/2 frame
Control Data Interface (Secondary FS)
REDG=0,
TDLA[3:0]=0000,
RDLA[3:0]=0000,
CD0A[3:0]=0000,
1 frame
Secondary FS
channel 0
Control
FL[3:0]=1110 (Frame length: 128 bits),
TDRE=0,
RDRE=0,
CD1E=0,
No.0
Slot
TDRA[3:0]=0000,
RDRA[3:0]=0000,
CD1A[3:0]=0000
1/2 frame
Normal FS