HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 256

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Memory Management Unit (MMU)
4.6
In order for TLB operations to be managed by software, TLB contents can be read or written to in
the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual
address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F200 0000 to
H'F2FF FFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F300 0000 to H'F3FF
FFFF. The V bit in the address array can also be accessed from the data array. Only longword
access is possible for both the address array and the data array. However, the instruction data
cannot be fetched from both arrays.
4.6.1
The address array is assigned to H'F200 0000 to H'F2FF FFFF. To access an address array, the 32-
bit address field (for read/write operations) and 32-bit data field (for write operations) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the VPN, V bit and ASID to be written to the address array (figure 4.14 (1)).
In the address field, specify the entry address for selecting the entry (bits 16 to 12), W for
selecting the way (bits 9 to 8) and H
in MMUCR indicates whether an EX-OR is taken of the entry address and ASID.
The following two operations can be used on the address array:
1. Address array read
2. TLB address array write
4.6.2
The data array is assigned to H'F300 0000 to H'F3FF FFFF. To access a data array, the 32-bit
address field (for read/write operations), and 32-bit data field (for write operations) must be
specified. The address section specifies information for selecting the entry to be accessed; the data
section specifies the longword data to be written to the data array (figure 4.14 (2)).
In the address section, specify the entry address for selecting the entry (bits 16 to 12), W for
selecting the way (bits 9 to 8), and H'F3 to indicate data array access (bits 31 to 24). The IX bit in
MMUCR indicates whether an EX-OR is taken of the entry address and ASID.
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VPN, V, and ASID are read from the TLB entry corresponding to the entry address and way
set in the address field.
The data specified in the data field are written to the TLB entry corresponding to the entry
address and way set in the address field.
Memory-Mapped TLB
Address Array
Data Array
′
F2 to indicate address array access (bits 31 to 24). The IX bit