HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 906

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
• Status Stage (Control-Out)
The control-out status stage starts with an IN token from the host. When an IN-token is received at
the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer
request interrupt is generated. The application recognizes from this interrupt that the status stage
has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable
bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be
transmitted to the host, and control transfer ends.
After the application has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
Rev. 3.00 Jan. 18, 2008 Page 844 of 1458
REJ09B0033-0300
USB Function Controller (USBF)
0-byte transmission to host
Set EP0i transmission
End of control transfer
(IFR0/EP0i TS = 1)
IN token reception
Figure 25.10
in EP0i FIFO?
complete flag
Valid data
USB function
Yes
ACK
Status Stage (Control-Out) Operation
No
NAK
Interrupt request
Interrupt request
Clear EP0i transmission
Write 1 to EP0i packet
End of control transfer
(TRG/EP0i PKTE = 1)
(IFR0/EP0i TR = 0)
Clear EP0i transfer
(IFR0/EP0i TS = 0)
complete flag
Application
request flag
enable bit