HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 116

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
2.5
2.5.1
(1)
All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the
sequential pipeline, almost all instructions can be executed in one cycle. All data items are handles
in longword (32 bits). Memory can be accessed in byte, word, or longword. In this case, Memory
byte or word data is sign-extended and operated on as longword data. Immediate data is sign-
extended to longword size for arithmetic operations (MOV, ADD, and CMP/EQ instructions) or
zero-extended to longword size for logical operations (TST, AND, OR, and XOR instructions).
(2)
Basic operations are executed between registers. In operations involving memory, data is first
loaded into a register (load/store architecture). However, bit manipulation instructions such as
AND are executed directly on memory.
(3)
Unconditional branch instructions are executed as delayed branches. With a delayed branch
instruction, the branch is made after execution of the instruction (called the slot instruction)
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made.
This LSI supports two types of conditional branch instructions: delayed branch instruction or
normal branch instruction.
Rev. 3.00 Jan. 18, 2008 Page 54 of 1458
REJ09B0033-0300
Example:
the
Instruction Length
Load/Store Architecture
Delayed Branching
Features of CPU Core Instructions
Instruction Execution Method
CPU
BRA
ADD
TARGET
R1, R0
; ADD is executed before branching to
TARGET