HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 449

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.7
The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin
(WEn (BEn)). This interface has 16-bit data pins and accesses SRAMs having upper and lower
byte selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byte-
selection SRAM interface is the same as that for the normal space interface. While in read access
of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin,
which is different from that for the normal space interface. The basic access timing is shown in
figure 9.32. In write access, data is written to the memory according to the timing of the byte-
selection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. Figure
9.33 shows the basic access timing. In write access, data is written to the memory according to the
timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write
must be acquired by setting the HW[1:0] bits in CSnWCR. Figure 9.34 shows the access timing
when a software wait is specified.
Figure 9.31
Byte-Selection SRAM Interface
16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2,
Address
RD/WR
DACK
WAIT
CKIO
Data
RD
BS
CS
Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits,
T1
Access Wait for 2nd Time and after = 1)
Tw
Tw
TB2
Twb
TB2
Rev. 3.00 Jan. 18, 2008 Page 387 of 1458
Twb
Section 9
TB2
Twb
Bus State Controller (BSC)
T2
REJ09B0033-0300