HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1175

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

33.2
The user break controller has the following registers. Refer to section 37, List of Registers, for
more details on the addresses and access size of these registers.
• Break address register A (BARA)
• Break address mask register A (BAMRA)
• Break bus cycle register A (BBRA)
• Break address register B (BARB)
• Break address mask register B (BAMRB)
• Break bus cycle register B (BBRB)
• Break data register B (BDRB)
• Break data mask register B (BDMRB)
• Break control register (BRCR)
• Execution times break register (BETR)
• Branch source register (BRSR)
• Branch destination register (BRDR)
• Break ASID register A (BASRA)
• Break ASID register B (BASRB)
33.2.1
BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition
in channel A.
Bit
31 to 0 BAA31 to
Bit Name
BAA0
Register Descriptions
Break Address Register A (BARA)
Initial
Value
All 0
R/W
R/W
Description
Break Address A
Store the address on the LAB or IAB specifying break
conditions of channel A.
Rev. 3.00 Jan. 18, 2008 Page 1113 of 1458
Section 33 User Break Controller (UBC)
REJ09B0033-0300