HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 948

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 26
26.3.16 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to control the Vsync interrupt of the LCD module. See also 26.3.20,
LCDC user specified interrupt control register (LDUINTR) and 26.3.21, LCDC user specified
interrupt line number register (LDUINTLNR) for interrupts. Note that operations by this register
setting and LCDC user specified interrupt control register (LDUINTR) setting are independent.
Rev. 3.00 Jan. 18, 2008 Page 886 of 1458
REJ09B0033-0300
Bit
15
14
13
12
Bit Name
MINTEN
FINTEN
VSINTEN
VEINTEN
LCD Controller (LCDC)
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Memory Access Interrupt Enable
Enables or disables an interrupt generation at the
start point of each vertical retrace line period for
VRAM access by LCDC.
0: Disables an interrupt generation at the start point
1: Enables an interrupt generation at the start point
Frame End Interrupt Enable
Enables or disables the generation of an interrupt
after the last pixel of a frame is output to LDC panel.
0: Disables an interrupt generation when the last
1: Enables an interrupt generation when the last
Vsync Starting Point Interrupt Enable
Enables or disables the generation of an interrupt at
the start point of LCDC's Vsync.
0: Interrupt at the start point of the Vsyncl is disabled
1: Interrupt at the start point of the Vsync is enabled
Vsync Ending Point Interrupt Enable
Enables or disables the generation of an interrupt at
the end point of LCDC's Vsync.
0: Interrupt at the end point of the Vsync signal is
1: Interrupt at the end point of the Vsync signal is
of each vertical retrace line period for VRAM
access
of each vertical retrace line period for VRAM
access
pixel of the frame is output
pixel of the frame is output
disabled
enabled