HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 830

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 24
24.3.1
24.3.2
The Hc Control register defines the operation mode for the host controller. The bits of this register
are amended only by the host controller driver (HCD) other than HCFS and RWC.
Rev. 3.00 Jan. 18, 2008 Page 768 of 1458
REJ09B0033-0300
Bit
31 to 8
7
6
5
4
3
2
1
0
Bit
31 to 11 
10
Hc Revision Register (USBHR)
Hc Control Register (USBHC)
Bit Name

Rev7
Rev6
Rev5
Rev4
Rev3
Rev2
Rev1
Rev0
Bit Name
RWE
USB Host Controller (USBH)
Initial
Value
All 0
0
0
0
1
0
0
0
0
Initial
Value
All 0
0
R/W
R
R
R
R
R
R
R
R
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Revision
These read only bits include the BCD expression of the
HCI specification version implemented for the host
controller. The value H'10 corresponds to version 1.0. All
HCI implementation complying with this specification have
the value of H'10.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Remote Wakeup Enable
This bit is set by HCD to enable/disable the remote
wakeup function at the same time as the detection of an
upstream resume signal.
This function is not supported. Be sure to write 0.